1. Field of the Invention
The disclosed embodiments relate to on-going reliability monitoring of integrated circuit (IC) chips and, more particularly, to an integrated circuit chip structure with a built-in self-test (BIST) circuit allowing for on-going reliability monitoring and, more specifically, allowing for in the field accelerated stress testing, the results of which can be used in system, method and computer program embodiments to generate IC chip performance degradation models and IC chip end of life predictions specific to different types of products.
2. Description of the Related Art
Various mechanisms associated with different classes of devices incorporated into integrated circuit (IC) chips can cause performance of the IC chips to degrade over time. Typically, in order to predict how IC chips in a given semiconductor technology will perform over time, all devices available in that given semiconductor technology are subjected to accelerated voltage and/or temperature stress tests in a laboratory environment at the wafer or module levels and/or in a test system environment. Then, based on the results of the accelerated stress testing, performance degradation models and end of life predictions for the IC chips in the given semiconductor technology are generated. Due to cost and time constraints such IC chip performance degradation models and IC chip end of life predictions are typically generated based on environmental assumptions (e.g., operating temperature, operating voltage, power-on-hours (POH), etc.) associated with only a selected sample of one or more products (e.g., for smart phones, tablet computers, etc.) that incorporate the IC chips. Then, the performance degradation models and end of life predictions are used across all products (i.e., applied to IC chips in the given semiconductor technology which are incorporated into any other products, such as laptop computers, desktop computers, servers, etc.).
Unfortunately, the environmental assumptions associated with the selected sample of products may be different then the actual environmental conditions in other products. For example, the operating temperature, operating voltage, power-on-hours (POH), etc. of IC chips may vary from product to product. Thus, the resulting IC chip performance degradation models and IC chip end of life predictions may not be applicable across all products. Therefore, it would be advantageous to be able to perform accelerated stress testing of all IC chips in a given semiconductor technology and to do so in the field on different types of products in order to eliminate any inaccurate environmental assumptions, thereby allowing for more accurate and continuously updated IC chip performance degradation models and IC chip end of life predictions that are specific to different types of products.